FIG. 1 (Prior Art) is a circuit diagram of a portion of a conventional non-volatile memory 1 called a "flash" memory. FIG. 2 (Prior Art) is a simplified top down diagram of the flash memory. Flash memory 1 has several bit transistors. The bit transistor 2 at the intersection of vertically extending metal bit line BL1 and horizontally extending word line WL2 is depicted in cross-section in FIGS. 3 and 4 (Prior Art). As shown in FIGS. 3 and 4, bit transistor 2 has a floating gate FG which is insulated from the overlying word line WL2 and metal bit line BL1. The rectangular cross-hatched features in FIG. 2 represent floating gates.
If, for example, floating gate FG is sufficiently "discharged" of electrons, then coupling the word line WL2 to a sufficiently positive potential (for example, 5.0 volts) will produce an adequately large electric field in the underlying silicon to cause a conductive channel to form between N type region 3 and N type region 4. If, on the other hand, floating gate FG is sufficiently "charged" with electrons, then coupling the word line WL2 to the sufficiently positive potential will not produce an adequately large electric field to cause a conductive channel to form between N type region 3 and N type region 4.
Accordingly, the second word of bits of flash memory 1 is read by driving word line WL2 with a positive voltage (for example, 5.0 volts) and by grounding the other word lines. Those bit transistors in the second word, the floating gates of which are discharged, are then conductive whereas the other bit transistors in the second word are not conductive. Each one of the bit lines BL1 through BLX+1 is driven with a positive voltage (such as 1.0 volts) and the current flowing through the bit line is sensed. If the bit line current is greater than 10 microamperes (for example, 100 microamperes), then the corresponding bit transistor in the selected word is determined to be conductive (i.e. "discharged"). If, on the other hand, the bit line current is less than 10 microamperes, then the corresponding bit transistor in the selected word is determined to be non-conductive (i.e. "charged"). The information content of each bit of the second word is read in this manner.
The flash memory 1 is "erased" of information by discharging all the floating gates at once (hence the term "flash"). Flash memory 1 is then "programmed" with information by charging selected ones of the floating gates and thereby leaving the other floating gates discharged. Discharging occurs by a phenomenon called "Fowler-Nordheim tunneling" whereas charging occurs by a phenomenon called "hot electron injection". See the following documents for further background information on Fowler-Nordheim tunneling, hot electron injection, and flash memory structures: U.S. Pat. No. 5,077,691 entitled "Flash EEPROM Array With Negative Gate Voltage Erase Operation; U.S. Pat. No. 4,698,787 entitled "Single Transistor Electrically Programmable Memory Device And Method; "Semiconductor Memories" by B. Prince, published by John Wiley & Sons, pages 183-187 and 586-608 (1983); "Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory" by S. Kobayashi et al., IEEE Journal of Solid-State Circuits, Vol. 29, No. 4, pages 454-460 (1994); and "Reliability Issues of Flash Memory Cells" by S. Aritome et al., Proceedings of the IEEE, Vol. 81, No. 5, pages 776-788 (1993). The subject matter of these documents is incorporated herein by reference.
Although such conventional flash memories function satisfactorily, ever more dense flash memory integrated circuits are sought. It is therefore desirable to make the individual bit transistors smaller and smaller. To decrease bit transistor geometries below about 0.25 microns (bit transistor gate length), however, advanced lithography tools including advanced steppers will likely be required. These tools are still being developed and are very expensive. It therefore is desirable to make smaller geometry bit transistors without using these advanced lithography tools.